1. Field of the Invention
The invention relates in general to a source driver circuit and a display panel incorporating the same, and more particularly to a source driver circuit for sampling and latching data in a time-sharing and multiplex manner, and a display panel incorporating the circuit.
2. Description of the Related Art
A low-temperature poly-silicon (LTPS) liquid crystal display is the developing mainstream of the current consumer electronic products, and is mainly applied to a display apparatus owing to its property of high integration and high image quality. Due to the enhancement in the stability of the current manufacturing process and the element property, the practicability of designing complicated circuits in the display apparatus has been greatly increased. In response to the integration trend of the build-in circuit in the display apparatus, simultaneously increasing the integration and the reliability of the image signal processing system provide a more flexible design and a wider application field of the display apparatus.
FIG. 1 (Related Art) is an internal block diagram showing a conventional source driver circuit 100. Referring to FIG. 1, the source driver circuit 100 serving as a build-in image processing circuit of a display apparatus mainly includes a horizontal shift register 108, a stage-by-stage sampling latch circuit 110, a line sequencing latch circuit 120 and a digital-to-analog converting circuit 130. The stage-by-stage sampling latch circuit 110 samples pixel data sent from a timing controller 106 under the control of the horizontal shift register 108. The line sequencing latch circuit 120 temporarily stores the sampled pixel data, and the digital-to-analog converting circuit 130 converts the pixel data into a pixel voltage with a suitable voltage level to be outputted to a pixel array (not shown).
FIG. 2 (Related Art) is an internal block diagram showing the stage-by-stage sampling latch circuit 110 and the line sequencing latch circuit 120 according to the prior art. Referring to FIG. 2, the stage-by-stage sampling latch circuit 110 includes a first sub-latch unit 111, a second sub-latch unit 112 and a third sub-latch unit 113. In a line time, each sub-latch unit samples six bits of pixel data, each of the pixel data DR0 to DR5 represents one bit of red pixel data, each of the pixel data DG0 to DG5 represents one bit of green pixel data and each of the pixel data DB0 to DB5 represents one bit of blue pixel data. Next, in a blanking time after the sampling, the stage-by-stage sampling latch circuit 110 transfers the sampled pixel data to the line sequencing latch circuit 120 so that the pixel data DR0 to DR5 are temporarily stored in a fourth sub-latch unit 124, the pixel data DG0 to DG5 are temporarily stored in a fifth sub-latch unit 125 and the pixel data DB0 to DB5 are temporarily stored in a sixth sub-latch unit 126. Thereafter, the pixel data stored in the fourth to sixth sub-latch units 124 to 126 are simultaneously outputted to the digital-to-analog converting circuit 130 via transmission channel sets 72, 74 and 76, respectively.
The total number of transmission channels required in the conventional source driver circuit 100 equals the product of the number of bits of the pixel data and the resolution of the digital signal. For example, in the mobile phone display having the wide viewing angle display screen (Quad-VGA), 240 (resolution)*18 (number of bits in a pixel)=4320 transmission channels are needed to simultaneously transmit the pixel data to the digital-to-analog converting circuit 130. The great number of transmission channels requires the relative large circuit layout area so that the size of the end product (e.g., the QVGA mobile phone) is large and the end product has the drawback of high power loss.